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CY7C1381CV25 CY7C1383CV25
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
Features
* Supports 133-MHz bus operations * 512K X 36/1M X 18 common I/O * 2.5V +/-5% core power supply (VDD) * 2.5V I/O supply (VDDQ) * Fast clock-to-output times -- 6.5 ns (133-MHz version) -- 7.5 ns (117-MHz version) -- 8.5 ns (100-MHz version) * Provide high-performance 2-1-1-1 access rate * User-selectable burst counter supporting Intel Pentium interleaved or linear burst sequences * Separate processor and controller address strobes * Synchronous self-timed write * Asynchronous output enable * Offered in JEDEC-standard 100-pin TQFP,119-ball BGA and 165-ball fBGA packages * JTAG boundary scan for BGA and fBGA packages * "ZZ" Sleep Mode option
Functional Description[1]
The CY7C1381CV25/CY7C1383CV25 is a 2.5V, 512K x 36 and 1M x 18 Synchronous Flow through SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE1), depth-expansion Chip Enables (CE2 and CE3[2]), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BWx, and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin. The CY7C1381CV25/CY7C1383CV25 allows either interleaved or linear burst sequences, selected by the MODE input pin. A HIGH selects an interleaved burst sequence, while a LOW selects a linear burst sequence. Burst accesses can be initiated with the Processor Address Strobe (ADSP) or the cache Controller Address Strobe (ADSC) inputs. Address advancement is controlled by the Address Advancement (ADV) input. Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor (ADSP) or Address Strobe Controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin (ADV). The CY7C1381CV25/CY7C1383CV25 operates from a +2.5V core power supply. All outputs also operate with a +2.5 supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible.
Selection Guide
133 MHz Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current 6.5 210 70 117 MHz 7.5 190 70 100 MHz 8.5 175 70 Unit ns mA mA
Notes: 1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com. 2. CE3, CE2 are for TQFP and 165 fBGA package only. 119 BGA is offered only in 1 Chip Enable.
Cypress Semiconductor Corporation Document #: 38-05241 Rev. *B
*
3901 North First Street
*
San Jose, CA 95134
* 408-943-2600 Revised April 19, 2004
CY7C1381CV25 CY7C1383CV25
Logic Block Diagram - CY7C1381CV25 (512K
A0, A1, A
1
ADDRESS REGISTER A[1:0]
MODE
ADV CLK
BURST Q1 COUNTER AND LOGIC Q0 CLR
ADSC ADSP DQD, DQPD BWD BYTE WRITE REGISTER DQC, DQPC BYTE WRITE REGISTER DQD, DQPD BYTE WRITE REGISTER DQC, DQPC BYTE WRITE REGISTER
BWC
A0, A1, A
BWB
ADDRESS DQB, DQPB REGISTER
BYTE
MODE
BWA BWE GW CE1 CE2 CE3 OE
WRITE REGISTER
A1 D1 A0 D0 ADV/LD C WRITE ADDRESS REGISTER
CLK CEN
C
CE
DQA, DQPA BYTE WRITE REGISTER
BURST LOGIC
Q1 A1' BYTE A0' Q0 WRITE REGISTER
DQA, DQPA BYTE WRITE REGISTER
DQB, DQPB
MEMORY ARRAY
SENSE AMPS
OUTPUT BUFFERS
DQs DQPA DQPB DQPC DQPD
ENABLE REGISTER
ZZ
ADV/LD BWA
SLEEP CONTROL
2
Logic Block Diagram -
A0,A1,A MODE
BWB
WRITE REGISTRY AND DATA COHERENCY CY7C1383CV25 LOGIC x CONTROL (1M
18)
WRITE DRIVERS
MEMORY ARRAY
S E N S E A M P S
D A T A S T E E R I N G
O U T P U T B U F F E R S E
INPUT REGISTERS
DQs DQPA DQPB
WE
ADDRESS REGISTER
A[1:0]
ADV CLK
ADSC
ADSP
OE CE1 CE2 CE3
ZZ
BURST Q1 COUNTER AND LOGIC READ LOGICQ0 CLR
INPUT E REGISTER
SLEEP CONTROL
BWB
DQB,DQPB WRITE REGISTER
DQB,DQPB WRITE DRIVER
MEMORY ARRAY
SENSE AMPS
OUTPUT BUFFERS
BWA BWE GW
DQA,DQPA WRITE REGISTER
DQA,DQPA WRITE DRIVER INPUT REGISTERS
DQs DQPA DQPB
CE1 CE2 CE3
OE
ENABLE REGISTER
ZZ
SLEEP CONTROL
Document #: 38-05241 Rev. *B
Page 2 of 35
CY7C1381CV25 CY7C1383CV25
Pin Configurations
100-pin TQFP Pinout
A A CE1 CE2 BWD BWC BWB BWA CE3 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A A A CE1 CE2 NC NC BWB BWA CE3 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A
DQPB DQB DQB VDDQ VSSQ DQB DQB DQB DQB VSSQ VDDQ DQB DQB VSS NC VDD ZZ DQA DQA VDDQ VSSQ DQA DQA DQA DQA VSSQ VDDQ DQA DQA DQPA NC NC NC VDDQ VSSQ NC NC DQB DQB VSSQ VDDQ DQB DQB NC VDD NC VSS DQB DQB VDDQ VSSQ DQB DQB DQPB NC VSSQ VDDQ NC NC NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
DQPC DQC DQC VDDQ VSSQ DQC DQC DQC DQC VSSQ VDDQ DQC DQC NC VDD NC VSS DQD DQD VDDQ VSSQ DQD DQD DQD DQD VSSQ VDDQ DQD DQD DQPD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
CY7C1381CV25 (512K x 36)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
CY7C1383CV25 (1M x 18)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
A NC NC VDDQ VSSQ NC DQPA DQA DQA VSSQ VDDQ DQA DQA VSS NC VDD ZZ DQA DQA VDDQ VSSQ DQA DQA NC NC VSSQ VDDQ NC NC NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
MODE A A A A A1 A0 NC NC VSS VDD
A A A A A A A A A
MODE A A A A A1 A0 NC NC VSS VDD
Document #: 38-05241 Rev. *B
A A A A A A A A A
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Page 3 of 35
CY7C1381CV25 CY7C1383CV25
Pin Configurations (continued)
119-ball BGA (1 Chip Enable with JTAG)
1 A B C D E F G H J K L M N P R T U VDDQ NC NC DQC DQC VDDQ DQC DQC VDDQ DQD DQD VDDQ DQD DQD NC NC VDDQ 2 A A A DQPC DQC DQC DQC DQC VDD DQD DQD DQD DQD DQPD A NC TMS CY7C1381CV25 (512K x 36) 3 4 5 A A ADSP A A VSS VSS VSS BWC VSS NC VSS BWD VSS VSS VSS MODE A TDI ADSC VDD NC CE1 OE ADV GW VDD CLK NC BWE A1 A0 VDD A TCK A A VSS VSS VSS BWB VSS NC VSS BWA VSS VSS VSS NC A TDO 6 A A A DQPB DQB DQB DQB DQB VDD DQA DQA DQA DQA DQPA A NC NC 7 VDDQ NC NC DQB DQB VDDQ DQB DQB VDDQ DQA DQA VDDQ DQA DQA NC ZZ VDDQ
CY7C1383CV25 (1M x 18) 1 A B C D E F G H J K L M N P R T U VDDQ NC NC DQB NC VDDQ NC DQB VDDQ NC DQB VDDQ DQB NC NC NC VDDQ 2 A A A NC DQB NC DQB NC VDD DQB NC DQB NC DQPB A A TMS 3 A A A VSS VSS VSS BWB VSS NC VSS VSS VSS VSS VSS MODE A TDI 4 ADSP ADSC VDD NC CE1 OE ADV GW VDD CLK NC BWE A1 A0 VDD NC TCK 5 A A A VSS VSS VSS VSS VSS NC VSS BWA VSS VSS VSS NC A TDO 6 A A A DQPA NC DQA NC DQA VDD NC DQA NC DQA NC A A NC 7 VDDQ NC NC NC DQA VDDQ DQA NC VDDQ DQA NC VDDQ NC DQA NC ZZ VDDQ
Document #: 38-05241 Rev. *B
Page 4 of 35
CY7C1381CV25 CY7C1383CV25
Pin Configurations (continued)
165-ball fBGA (3 Chip Enable)
CY7C1381CV25 (512K x 36)
1 A B C D E F G H J K L M N P R
NC / 288M NC DQPC DQC DQC DQC DQC NC DQD DQD DQD DQD DQPD NC MODE
2
A A NC DQC DQC DQC DQC VSS DQD DQD DQD DQD NC NC / 72M NC / 36M
3
CE1 CE2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A
4
BWC BWD VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS
A
5
BWB BWA VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI
TMS
6
CE3 CLK
7
BWE GW
8
ADSC OE
9
ADV ADSP VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A
A
10
A A NC DQB DQB DQB DQB NC DQA DQA DQA DQA NC A A
11
NC NC / 144M DQPB DQB DQB DQB DQB ZZ DQA DQA DQA DQA DQPA A A
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
A A1
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDO TCK
VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS
A
A
A0
A
CY7C1383CV25 (1M x 18)
1 A B C D E F G H J K L M N P R
NC / 288M NC NC NC NC NC NC VSS DQB DQB DQB DQB DQPB NC MODE
2
A A NC DQB DQB DQB DQB VSS NC NC NC NC NC NC / 72M NC / 36M
3
CE1 CE2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A
4
BWB NC VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS
A
5
NC BWA VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI
TMS
6
CE3 CLK
7
BWE GW
8
ADSC OE
9
ADV ADSP VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A
A
10
A A NC NC NC NC NC NC DQA DQA DQA DQA NC A A
11
A NC / 144M DQPA DQA DQA DQA DQA ZZ NC NC NC NC NC A A
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
A
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDO TCK
VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS
A
A1 A0
A
A
Document #: 38-05241 Rev. *B
Page 5 of 35
CY7C1381CV25 CY7C1383CV25
CY7C1381CV25-Pin Definitions
Name A0, A1, A TQFP (3-Chip Enable) 37,36,32,33,34, 35,42,43,44,45, 46,47,48,49,50, 81,82,99,100 93,94,95,96 BGA (1-Chip Enable) P4,N4,A2,B2,C2 ,R2,A3,B3,C3,T 3,T4,A5,B5,C5, T5,A6,B6,C6,R6 L5,G5,G3,L3 fBGA (3-Chip Enable) R6,P6,A2,A10, B2,B10,N6,P3, P4,P8,P9,P10, P11,R3,R4,R8, R9,R10,R11 B5,A5,A4,B4 I/O Description
InputAddress Inputs used to select one of the Synchronous 512K address locations. Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3[2] are sampled active. A[1:0] feed the 2-bit counter. InputByte Write Select Inputs, active LOW. Synchronous Qualified with BWE to conduct byte writes to the SRAM. Sampled on the rising edge of CLK. InputGlobal Write Enable Input, active LOW. Synchronous When asserted LOW on the rising edge of CLK, a global write is conducted (ALL bytes are written, regardless of the values on BW[A:D]and BWE). InputClock Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst counter when ADV is asserted LOW, during a burst operation.
BWA,BWB BWC,BWD GW
88
H4
B7
CLK
89
K4
B6
CE1
98
E4
A3
InputChip Enable 1 Input, active LOW. Sampled Synchronous on the rising edge of CLK. Used in conjunction with CE2 and CE3[2] to select/deselect the device. ADSP is ignored if CE1 is HIGH. InputChip Enable 2 Input, active HIGH. Synchronous Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE3[2] to select/deselect the device. InputChip Enable 3 Input, active LOW. Sampled Synchronous on the rising edge of CLK. Used in conjunction with CE1 and CE2 to select/deselect the device. InputOutput Enable, asynchronous input, Asynchronous active LOW. Controls the direction of the I/O pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. OE is masked during the first clock of a read cycle when emerging from a deselected state. InputAdvance Input signal, sampled on the Synchronous rising edge of CLK. When asserted, it automatically increments the address in a burst cycle. InputAddress Strobe from Processor, sampled Synchronous on the rising edge of CLK, active LOW. When asserted LOW, addresses presented to the device are captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH
CE2
97
-
B3
CE3[2]
92
-
A6
OE
86
F4
B8
ADV
83
G4
A9
ADSP
84
A4
B9
Document #: 38-05241 Rev. *B
Page 6 of 35
CY7C1381CV25 CY7C1383CV25
CY7C1381CV25-Pin Definitions (continued)
Name ADSC TQFP (3-Chip Enable) 85 BGA (1-Chip Enable) B4 fBGA (3-Chip Enable) A8 I/O Description
InputAddress Strobe from Controller, sampled Synchronous on the rising edge of CLK, active LOW. When asserted LOW, addresses presented to the device are captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. InputByte Write Enable Input, active LOW. Synchronous Sampled on the rising edge of CLK. This signal must be asserted LOW to conduct a byte write. InputZZ "sleep" Input, active HIGH. When Asynchronous asserted HIGH places the device in a non-time-critical "sleep" condition with data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ pin has an internal pull-down. I/OBidirectional Data I/O lines. As inputs, they Synchronous feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the addresses presented during the previous clock rise of the read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQP[A:D] are placed in a tri-state condition.The outputs are automatically tri-stated during the data portion of a write sequence, during the first clock when emerging from a deselected state, and when the device is deselected, regardless of the state of OE. I/OBidirectional Data Parity I/O Lines. Synchronous Functionally, these signals are identical to DQs. During write sequences, DQP[A:D] is controlled by BW[A:D] correspondingly. Input-Static Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDD or left floating selects interleaved burst sequence. This is a strap pin and should remain static during device operation. Mode Pin has an internal pull-up.
BWE
87
M4
A7
ZZ
64
T7
H11
DQs
52,53,56,57,58, 59,62,63,68,69, 72,73,74,75,78, 79,2,3,6,7,8,9, 12,13,18,19,22, 23,24,25,28,29
K6,L6,M6,N6,K7 M11,L11,K11, J11,J10,K10, ,L7,N7,P7,E6,F 6,G6,H6,D7,E7, L10,M10,D10, G7,H7,D1,E1,G E10,F10,G10, 1,H1,E2,F2,G2, D11,E11,F11, G11,D1,E1, H2,K1,L1,N1,P1 F1,G1,D2,E2, ,K2,L2,M2,N2 F2,G2,J1,K1, L1,M1,J2, K2,L2,M2,
DQP[A:D]
51,80,1,30
P6,D6,D2,P2
N11,C11,C1,N1
MODE
31
R3
R1
VDD
15,41,65,91
J2,C4,J4,R4,J6
D4,D8,E4, E8,F4,F8, G4,G8,H4, H8,J4,J8, K4,K8,L4, L8,M4,M8
Power Supply Power supply inputs to the core of the device.
Document #: 38-05241 Rev. *B
Page 7 of 35
CY7C1381CV25 CY7C1383CV25
CY7C1381CV25-Pin Definitions (continued)
Name VDDQ TQFP (3-Chip Enable) 4,11,20,27, 54,61,70,77 BGA (1-Chip Enable) A1,F1,J1,M1,U1 , A7,F7,J7,M7,U7 fBGA (3-Chip Enable) C3,C9,D3, D9,E3,E9, F3,F9,G3, G9,J3,J9, K3,K9,L3, L9,M3,M9, N3,N9 C4,C5,C6, C7,C8,D5, D6,D7,E5, E6,E7,F5, F6,F7,G5, G6,G7,H5, H6,H7,J5, J6,J7,K5,K6,K7, L5,L6,L7,M5,M6 ,M7,N4,N8 P7 I/O I/O Power Supply Description Power supply for the I/O circuitry.
VSS
17,40,67,90
H2,D3,E3,F3,H3 ,K3, M3,N3, P3,D5,E5,F5,H5 ,K5, M5,N5,P5
Ground
Ground for the core of the device.
VSSQ TDO
5,10,21,26, 55,60,71,76 -
U5
I/O Ground JTAG serial output Synchronous
Ground for the I/O circuitry. Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the JTAG feature is not being utilized, this pin should be left unconnected. This pin is not available on TQFP packages.
TDI
-
U3
P5
JTAG serial Serial data-In to the JTAG circuit. Sampled input on the rising edge of TCK. If the JTAG feature Synchronous is not being utilized, this pin can be left floating or connected to VDD through a pull up resistor. This pin is not available on TQFP packages. JTAG serial Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature input Synchronous is not being utilized, this pin can be disconnected or connected to VDD. This pin is not available on TQFP packages. JTAG-Clock Clock input to the JTAG circuitry. If the JTAG feature is not being utilized, this pin must be connected to VSS. This pin is not available on TQFP packages. No Connects. Not internally connected to the die. 18M, 36M, 72M, 144M and 288M are address expansion pins are not internally connected to the die.
TMS
-
U2
R5
TCK
-
U4
R7
NC
16,38,39,66
B1,C1,R1,T1,T2 A1,A11,B1, ,J3,D4,L4,J5,R5 B11,C2,C10,H1, ,T6,U6,B7,C7,R H3,H9, 7 H10,N2,N5,N7, N10,P1,P2,R2 -
-
VSS/DNU
14
Ground/DNU This pin can be connected to Ground or should be left floating.
Document #: 38-05241 Rev. *B
Page 8 of 35
CY7C1381CV25 CY7C1383CV25
CY7C1383CV25:Pin Definitions
Name A0, A1, A TQFP (3-Chip Enable) 37,36,32,33,34, 35,42,43,44,45, 46,47,48,49,50, 80,81,82,99,100 BGA (1-Chip Enable) P4,N4,A2,B2, C2,R2,T2,A3, B3,C3,T3,A5, B5,C5,T5,A6, B6,C6,R6,T6 L5,G3 fBGA (3-Chip Enable) R6,P6,A2, A10,A11,B2, B10,N6,P3,P4, P8,P9,P10, P11,R3,R4, R8,R9,R10,R11 B5,A4 I/O InputSynchronous Description Address Inputs used to select one of the 1M address locations. Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3[2] are sampled active. A[1:0] feed the 2-bit counter. Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM. Sampled on the rising edge of CLK. Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global write is conducted (ALL bytes are written, regardless of the values on BW[A:B] and BWE). Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be asserted LOW to conduct a byte write. Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst counter when ADV is asserted LOW, during a burst operation. Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 and CE3[2] to select/deselect the device. ADSP is ignored if CE1 is HIGH. Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE3[2] to select/deselect the device. Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE2 to select/deselect the device.
BWA,BWB
93,94
InputSynchronous
GW
88
H4
B7
InputSynchronous
BWE
87
M4
A7
InputSynchronous
CLK
89
K4
B6
InputClock
CE1
98
E4
A3
InputSynchronous
CE2
97
-
B3
InputSynchronous
CE3[2]
92
-
A6
InputSynchronous
OE
86
F4
B8
InputOutput Enable, asynchronous input, Asynchronous active LOW. Controls the direction of the I/O pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. OE is masked during the first clock of a read cycle when emerging from a deselected state. InputSynchronous Advance Input signal, sampled on the rising edge of CLK. When asserted, it automatically increments the address in a burst cycle.
ADV
83
G4
A9
Document #: 38-05241 Rev. *B
Page 9 of 35
CY7C1381CV25 CY7C1383CV25
CY7C1383CV25:Pin Definitions (continued)
Name ADSP TQFP (3-Chip Enable) 84 BGA (1-Chip Enable) A4 fBGA (3-Chip Enable) B9 I/O InputSynchronous Description Address Strobe from Processor, sampled on the rising edge of CLK, active LOW. When asserted LOW, addresses presented to the device are captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH Address Strobe from Controller, sampled on the rising edge of CLK, active LOW. When asserted LOW, addresses presented to the device are captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized.
ADSC
85
B4
A8
InputSynchronous
ZZ
64
T7
H11
InputZZ "sleep" Input, active HIGH. When Asynchronous asserted HIGH places the device in a non-time-critical "sleep" condition with data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ pin has an internal pull-down. I/OSynchronous Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the addresses presented during the previous clock rise of the read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQP[A:B] are placed in a tri-state condition.The outputs are automatically tri-stated during the data portion of a write sequence, during the first clock when emerging from a deselected state, and when the device is deselected, regardless of the state of OE. Bidirectional Data Parity I/O Lines. Functionally, these signals are identical to DQs. During write sequences, DQP[A:B] is controlled by BW[A:B] correspondingly. Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDD or left floating selects interleaved burst sequence. This is a strap pin and should remain static during device operation. Mode Pin has an internal pull-up.
DQs
58,59,62,63,68, P7,K7,G7,E7,F6 J10,K10, 69,72,73,8,9,12, ,H6,L6,N6,D1,H L10,M10, 13, 1,L1,N1,E2,G2, D11,E11, 18,19,22,23 K2,M2 F11,G11,J1,K1, L1,M1, D2,E2,F2, G2
DQP[A:B]
74,24
D6,P2
C11,N1
I/OSynchronous
MODE
31
R3
R1
Input-Static
Document #: 38-05241 Rev. *B
Page 10 of 35
CY7C1381CV25 CY7C1383CV25
CY7C1383CV25:Pin Definitions (continued)
Name VDD TQFP (3-Chip Enable) 15,41,65,91 BGA (1-Chip Enable) C4,J2,J4,J6,R4 fBGA (3-Chip Enable) D4,D8,E4, E8,F4,F8, G4,G8, H4,H8,J4, J8,K4,K8, L4,L8,M4, M8 C3,C9,D3, D9,E3,E9, F3,F9,G3, G9,J3,J9, K3,K9,L3, L9,M3,M9, N3,N9 C4,C5,C6, C7,C8,D5, D6,D7,E5, E6,E7,F5, F6,F7,G5, G6,G7,H1, H2,H5,H6, H7,J5,J6,J7,K5, K6,K7,L5,L6,L7, M5, M6,M7,N4, N8 P7 I/O Description
Power Supply Power supply inputs to the core of the device.
VDDQ
4,11,20,27, 54,61,70,77
A1,A7,F1,F7,J1, J7,M1,M7,U1,U 7
I/O Power Supply
Power supply for the I/O circuitry.
VSS
17,40,67,90
D3,D5,E3,E5,F3 ,F5,G5,H3, H5,K3,K5,L3,M3 , M5,N3, N5,P3,P5
Ground
Ground for the core of the device.
VSSQ TDO
5,10,21,26, 55,60,71,76, -
U5
I/O Ground JTAG serial output Synchronous
Ground for the I/O circuitry. Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the JTAG feature is not being utilized, this pin should be left unconnected. This pin is not available on TQFP packages. Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is not being utilized, this pin can be left floating or connected to VDD through a pull up resistor. This pin is not available on TQFP packages. Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is not being utilized, this pin can be disconnected or connected to VDD. This pin is not available on TQFP packages. Clock input to the JTAG circuitry. If the JTAG feature is not being utilized, this pin must be connected to VSS. This pin is not available on TQFP packages.
TDI
-
U3
P5
JTAG serial input Synchronous
TMS
-
U2
R5
JTAG serial input Synchronous
TCK
-
U4
R7
JTAG-Clock
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CY7C1381CV25 CY7C1383CV25
CY7C1383CV25:Pin Definitions (continued)
Name NC TQFP (3-Chip Enable) 1,2,3,6,7,16,25, 28,29,30,38,39, 51,52,53,56,57, 66,75,78,79,95, 96 BGA (1-Chip Enable) B1,B7,C1,C7,D 2,D4,D7,E1,E6, H2,F2,G1,G6,H 7,J3,J5,K1,K6,L 4,L2,L7,M6,N2, N7,L7,P1,P6,R1 ,R5,R7,T1,T4,U 6 fBGA (3-Chip Enable) A1,A5,B1, B4,B11,C1,C2,C 10,D1,D10,E1,E 10,F1,F10,G1,G 10,H3,H9,H10,J 2,J11,K2,K11, L2,L11,M2,M11, N2,N5,N7,N10, N11,P1,P2,R2 I/O Description No Connects. Not internally connected to the die. 36M, 72M, 144M and 288M are address expansion pins are not internally connected to the die.
VSS/DNU
14
Ground/DNU
This pin can be connected to Ground or should be left floating.
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CY7C1381CV25 CY7C1383CV25
Functional Overview
All synchronous inputs pass through input registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (t CDV) is 6.5 ns (133-MHz device). The CY7C1381CV25 supports secondary cache in systems utilizing either a linear or interleaved burst sequence. The interleaved burst order supports Pentium(R) and i486 processors. The linear burst sequence is suited for processors that utilize a linear burst sequence. The burst order is user-selectable, and is determined by sampling the MODE input. Accesses can be initiated with either the Processor Address Strobe (ADSP) or the Controller Address Strobe (ADSC). Address advancement through the burst sequence is controlled by the ADV input. A two-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. Byte write operations are qualified with the Byte Write Enable (BWE) and Byte Write Select (BWX) inputs. A Global Write Enable (GW) overrides all byte write inputs and writes data to all four bytes. All writes are simplified with on-chip synchronous self-timed write circuitry. Three synchronous Chip Selects (CE1, CE2, CE3[2]) and an asynchronous Output Enable (OE) provide for easy bank selection and output tri-state control. ADSP is ignored if CE1 is HIGH. Single Read Accesses A single read access is initiated when the following conditions are satisfied at clock rise: (1) CE1, CE2, and CE3[2] are all asserted active, and (2) ADSP or ADSC is asserted LOW (if the access is initiated by ADSC, the write inputs must be deasserted during this first cycle). The address presented to the address inputs is latched into the address register and the burst counter/control logic and presented to the memory core. If the OE input is asserted LOW, the requested data will be available at the data outputs a maximum to tCDV after clock rise. ADSP is ignored if CE1 is HIGH. Single Write Accesses Initiated by ADSP This access is initiated when the following conditions are satisfied at clock rise: (1) CE1, CE2, CE3[2] are all asserted active, and (2) ADSP is asserted LOW. The addresses presented are loaded into the address register and the burst inputs (GW, BWE, and BWX)are ignored during this first clock cycle. If the write inputs are asserted active ( see Write Cycle Descriptions table for appropriate states that indicate a write) on the next clock rise,the appropriate data will be latched and written into the device.Byte writes are allowed. All I/Os are tri-stated during a byte write.Since this is a common I/O device, the asynchronous OE input signal must be deasserted and the I/Os must be tri-stated prior to the presentation of data to DQs. As a safety precaution, the data lines are tri-stated once a write cycle is detected, regardless of the state of OE. Single Write Accesses Initiated by ADSC This write access is initiated when the following conditions are satisfied at clock rise: (1) CE1, CE2, and CE3[2] are all asserted active, (2) ADSC is asserted LOW, (3) ADSP is deasserted HIGH, and (4) the write input signals (GW, BWE, and BWX) indicate a write access. ADSC is ignored if ADSP is active LOW. The addresses presented are loaded into the address register and the burst counter/control logic and delivered to the memory core. The information presented to DQ[A:D] will be written into the specified address location. Byte writes are allowed. All I/Os are tri-stated when a write is detected, even a byte write. Since this is a common I/O device, the asynchronous OE input signal must be deasserted and the I/Os must be tri-stated prior to the presentation of data to DQs. As a safety precaution, the data lines are tri-stated once a write cycle is detected, regardless of the state of OE. Burst Sequences The CY7C1381CV25 provides an on-chip two-bit wraparound burst counter inside the SRAM. The burst counter is fed by A[1:0], and can follow either a linear or interleaved burst order. The burst order is determined by the state of the MODE input. A LOW on MODE will select a linear burst sequence. A HIGH on MODE will select an interleaved burst order. Leaving MODE unconnected will cause the device to default to a interleaved burst sequence.
Interleaved Burst Address Table (MODE = Floating or VDD)
First Address A1: A0 00 01 10 11 Second Address A1: A0 01 00 11 10 Third Address A1: A0 10 11 00 01 Fourth Address A1: A0 11 10 01 00
Linear Burst Address Table (MODE = GND)
First Address A1: A0 00 01 10 11 Sleep Mode The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation "sleep" mode. Two clock cycles are required to enter into or exit from this "sleep" mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the "sleep" mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the "sleep" mode. CE1, CE2, CE3[2], ADSP, and ADSC must remain inactive for the duration of tZZREC after the ZZ input returns LOW. Second Address A1: A0 01 10 11 00 Third Address A1: A0 10 11 00 01 Fourth Address A1: A0 11 00 01 10
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CY7C1381CV25 CY7C1383CV25
ZZ Mode Electrical Characteristics
Parameter IDDZZ tZZS tZZREC tZZI tRZZI Description Snooze mode standby current Device operation to ZZ ZZ recovery time ZZ active to snooze current ZZ Inactive to exit snooze current Test Conditions ZZ > VDD - 0.2V ZZ > VDD - 0.2V ZZ < 0.2V This parameter is sampled This parameter is sampled Min. Max. 60 2tCYC 2tCYC 2tCYC 0 Unit mA ns ns ns ns
Truth Table[ 3, 4, 5, 6, 7]
Cycle Description Deselected Cycle, Power-down Deselected Cycle, Power-down Deselected Cycle, Power-down Deselected Cycle, Power-down Deselected Cycle, Power-down Snooze Mode, Power-down Read Cycle, Begin Burst Read Cycle, Begin Burst Write Cycle, Begin Burst Read Cycle, Begin Burst Read Cycle, Begin Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Write Cycle, Continue Burst Write Cycle, Continue Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Write Cycle, Suspend Burst Write Cycle, Suspend Burst ADDRESS Used CE1 CE2 CE3 ZZ None H X X L None None None None None External External External External External Next Next Next Next Next Next Current Current Current Current Current Current L L L X X L L L L L X X H H X H X X H H X H L X L X X H H H H H X X X X X X X X X X X X X H X X X L L L L L X X X X X X X X X X X X L L L L H L L L L L L L L L L L L L L L L L ADSP X L L H H X L L H H H H H X X H X H H X X H X ADSC L X X L L X X X L L L H H H H H H H H H H H H ADV WRITE X X X X X X X X X X X L L L L L L H H H H H H X X X X X X X X L H H H H H H L L H H H H L L OE X X X X X X L H X L H L H L H X X L H L H X X CLK DQ
L-H Tri-State L-H Tri-State L-H Tri-State L-H Tri-State L-H Tri-State X L-H L-H L-H L-H L-H L-H L-H L-H Tri-State Q Tri-State D Q Tri-State Q Tri-State Q
L-H Tri-State L-H D L-H D L-H Q L-H Tri-State L-H Q L-H Tri-State L-H D L-H D
Notes: 3. X="Don't Care." H = Logic HIGH, L = Logic LOW. 4. WRITE = L when any one or more Byte Write enable signals and BWE = L or GW= L. WRITE = H when all Byte write enable signals, BWE, GW = H. 5. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock. 6. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a don't care for the remainder of the write cycle. 7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are Tri-State when OE is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
3
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CY7C1381CV25 CY7C1383CV25
Partial Truth Table for Read/Write[3, 8]
Function (CY7C1381CV25) Read Read Write Byte A (DQA, DQPA) Write Byte B(DQB, DQPB) Write Bytes A, B (DQA, DQB, DQPA, DQPB) Write Byte C (DQC, DQPC) Write Bytes C, A (DQC, DQA, DQPC, DQPA) Write Bytes C, B (DQC, DQB, DQPC, DQPB) Write Bytes C, B, A (DQC, DQB, DQA, DQPC, DQPB, DQPA) Write Byte D (DQD, DQPD) Write Bytes D, A (DQD, DQA, DQPD, DQPA) Write Bytes D, B (DQD, DQA, DQPD, DQPA) Write Bytes D, B, A (DQD, DQB, DQA, DQPD, DQPB, DQPA) Write Bytes D, B (DQD, DQB, DQPD, DQPB) Write Bytes D, B, A (DQD, DQC, DQA, DQPD, DQPC, DQPA) Write Bytes D, C, A (DQD, DQB, DQA, DQPD, DQPB, DQPA) Write All Bytes Write All Bytes GW H H H H H H H H H H H H H H H H H L BWE H L L L L L L L L L L L L L L L L X BWD X H H H H H H H H L L L L L L L L X BWC X H H H H L L L L H H H H L L L L X BWB X H H L L H H L L H H L L H H L L X BWA X H L H L H L H L H L H L H L H L X
Note: 8. Table only lists a partial listing of the byte write combinations. Any Combination of BWX is valid Appropriate write will be done based on which byte write is active.
Truth Table for Read/Write[3]
Function (CY7C1383CV25) Read Read Write Byte A - (DQA and DQPA) Write Byte B - (DQB and DQPB) Write All Bytes Write All Bytes GW H H H H H L BWE H L L L L X BWB X H H L L X BWA X H L H L X
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CY7C1381CV25 CY7C1383CV25
IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1381CV25 incorporates a serial boundary scan test access port (TAP). This port operates in accordance with IEEE Standard 1149.1-1990 but does not have the set of functions required for full 1149.1 compliance. These functions from the IEEE specification are excluded because their inclusion places an added delay in the critical speed path of the SRAM. Note that the TAP controller functions in a manner that does not conflict with the operation of other devices using 1149.1 fully compliant TAPs. The TAP operates using JEDEC-standard 2.5V I/O logic levels. The CY7C1381CV25 contains a TAP controller, instruction register, boundary scan register, bypass register, and ID register. Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW(VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately be connected to VDD through a pull-up resistor. TDO should be left unconnected. Upon power-up, the device will come up in a reset state which will not interfere with the operation of the device. Test MODE SELECT (TMS) The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. It is allowable to leave this ball unconnected if the TAP is not used. The ball is pulled up internally, resulting in a logic HIGH level. Test Data-In (TDI) The TDI ball is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register, see Figure . TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) of any register. (See Tap Controller Block Diagram.) Test Data-Out (TDO) The TDO output ball is used to serially clock data-out from the registers. The output is active depending upon the current state of the TAP state machine. The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. (See Tap Controller State Diagram.)
TAP Controller Block Diagram
0 Bypass Register
210
TAP Controller State Diagram
1 TEST-LOGIC RESET 0 0 RUN-TEST/ IDLE 1 SELECT DR-SCAN 0 1 CAPTURE-DR 0 SHIFT-DR 1 EXIT1-DR 0 PAUSE-DR 1 0 EXIT2-DR 1 UPDATE-DR 1 0 0 0 1 0 1 1 SELECT IR-SCAN 0 CAPTURE-IR 0 SHIFT-IR 1 EXIT1-IR 0 PAUSE-IR 1 EXIT2-IR 1 UPDATE-IR 1 0 0 1 0 1
TDI
Selection Circuitry
Instruction Register
31 30 29 . . . 2 1 0
Selection
Circuitry
TDO
Identification Register
x. . . . .210
Boundary Scan Register
TCK TMS TAP CONTROLLER
Performing a TAP Reset A RESET is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating. At power-up, the TAP is reset internally to ensure that TDO comes up in a High-Z state. TAP Registers Registers are connected between the TDI and TDO balls and allow data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction register. Data is serially loaded into the TDI ball on the rising edge of TCK. Data is output on the TDO ball on the falling edge of TCK.
The 0/1 next to each state represents the value of TMS at the rising edge of TCK. Test Access Port (TAP) Test Clock (TCK) The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK.
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CY7C1381CV25 CY7C1383CV25
Instruction Register Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO balls as shown in the Tap Controller Block Diagram. Upon power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section. When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary "01" pattern to allow for fault isolation of the board-level serial test data path. Bypass Register To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit register that can be placed between the TDI and TDO balls. This allows data to be shifted through the SRAM with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed. Boundary Scan Register The boundary scan register is connected to all the input and bidirectional balls on the SRAM. The x36 configuration has a 70-bit-long register and the x18 configuration has a 51-bit long register. The boundary scan register is loaded with the contents of the RAM I/O ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO balls when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the I/O ring. The Boundary Scan Order tables show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO. Identification (ID) Register The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in the Identification Register Definitions table. TAP Instruction Set Overview Eight different instructions are possible with the three bit instruction register. All combinations are listed in the Instruction Codes table. Three of these instructions are listed as RESERVED and should not be used. The other five instructions are described in detail below. The TAP controller used in this SRAM is not fully compliant to the 1149.1 convention because some of the mandatory 1149.1 instructions are not fully implemented. The TAP controller cannot be used to load address data or control signals into the SRAM and cannot preload the I/O buffers. The SRAM does not implement the 1149.1 commands EXTEST or INTEST or the PRELOAD portion of SAMPLE/PRELOAD; rather, it performs a capture of the I/O ring when these instructions are executed. Document #: 38-05241 Rev. *B Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO balls. To execute the instruction once it is shifted in, the TAP controller needs to be moved into the Update-IR state. EXTEST EXTEST is a mandatory 1149.1 instruction which is to be executed whenever the instruction register is loaded with all 0s. EXTEST is not implemented in this SRAM TAP controller, and therefore this device is not compliant to 1149.1. The TAP controller does recognize an all-0 instruction. When an EXTEST instruction is loaded into the instruction register, the SRAM responds as if a SAMPLE/PRELOAD instruction has been loaded. There is one difference between the two instructions. Unlike the SAMPLE/PRELOAD instruction, EXTEST places the SRAM outputs in a High-Z state. IDCODE The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO balls and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register upon power-up or whenever the TAP controller is given a test logic reset state. SAMPLE Z The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO balls when the TAP controller is in a Shift-DR state. It also places all SRAM outputs into a High-Z state. SAMPLE/PRELOAD SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The PRELOAD portion of this instruction is not implemented, so the device TAP controller is not fully 1149.1 compliant. When the SAMPLE/PRELOAD instruction is loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and bidirectional balls is captured in the boundary scan register. The user must be aware that the TAP controller clock can only operate at a frequency up to 10 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output will undergo a transition. The TAP may then try to capture a signal while in transition (metastable state). This will not harm the device, but there is no guarantee as to the value that will be captured. Repeatable results may not be possible. To guarantee that the boundary scan register will capture the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller's capture setup plus hold time (tCS plus tCH). The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still
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CY7C1381CV25 CY7C1383CV25
possible to capture all other signals and simply ignore the value of the CLK captured in the boundary scan register. Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO balls. Note that since the PRELOAD part of the command is not implemented, putting the TAP to the Update-DR state while performing a SAMPLE/PRELOAD instruction will have the same effect as the Pause-DR command. BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO balls. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions.
TAP Timing
1 Test Clock (TCK)
t TMSS
2
3
4
5
6
t TH t TMSH
t TL
t CYC
Test Mode Select (TMS)
t TDIS t TDIH
Test Data-In (TDI)
t TDOV t TDOX
Test Data-Out (TDO) DON'T CARE UNDEFINED
TAP AC Switching Characteristics Over the operating Range[9, 10]
Parameter Clock TCK Clock Cycle Time TCK Clock Frequency TCK Clock HIGH time TCK Clock LOW time Output Times TCK Clock LOW to TDO Valid TCK Clock LOW to TDO Invalid Setup Times TMS Set-Up to TCK Clock Rise TDI Set-Up to TCK Clock Rise Capture Set-Up to TCK Rise Hold Times TMS hold after TCK Clock Rise TDI Hold after Clock Rise Capture Hold after Clock Rise Symbol tTCYC tTF tTH tTL tTDOV tTDOX tTMSS tTDIS tCS tTMSH tTDIH tCH Min. 100 10 40 40 20 0 10 10 10 10 10 10 Max Units ns MHz ns ns ns ns ns ns
ns ns ns
Notes: 9. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register. 10. Test conditions are specified using the load in TAP AC test Conditions. T.R/tF = 1ns
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CY7C1381CV25 CY7C1383CV25
2.5V TAP AC Test Conditions
Input pulse levels ...... ........................................VSS to 2.5V Input rise and fall time...................................................... 1ns Input timing reference levels .........................................1.25V Output reference levels.................................................1.25V Test load termination supply voltage.............................1.25V
2.5V TAP AC Output Load Equivalent
1.25V 50 TDO Z O= 50 20pF
TAP DC Electrical Characteristics And Operating Conditions
(0C < TA < +70C; Vdd = 2.5V 0.125V unless otherwise noted)[11] PARAMETER VOH1 VOH2 VOL1 VOL2 VIH VIL IX DESCRIPTION TEST CONDITIONS MIN 2.0 2.1 0.4 VDDQ = 2.5V VDDQ = 2.5V VDDQ = 2.5V GND < VIN < VDDQ 1.7 -0.3 -5 0.2 VDD + 0.3 0.7 5 MAX UNITS V V V V V V A
Output HIGH Voltage IOH = -1.0 mA, VDDQ = 2.5V Output HIGH Voltage IOH = -100 A,VDDQ = 2.5V Output LOW Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Load Current IOL = 8.0 mA, VDDQ = 2.5V IOL = 100 A
Note: 11. All voltages referenced to VSS (GND).
Identification Register Definitions
INSTRUCTION FIELD Revision Number (31:29) Device Depth (28:24) Device Width (23:18) Cypress Device ID (17:12) Cypress JEDEC ID Code (11:1) ID Register Presence Indicator (0) CY7C1381CV25 (512KX36) 010 01011 000001 100101 00000110100 1 CY7C1383CV25 (1MX18) 010 01011 000001 010101 00000110100 1 DESCRIPTION Describes the version number. Reserved for Internal Use Defines memory type and architecture Defines width and density Allows unique identification of SRAM vendor. Indicates the presence of an ID register.
Scan Register Sizes
REGISTER NAME Instruction Bypass Bypass ID Boundary Scan Order BIT SIZE(X36) 3 1 32 72 BIT SIZE(X18) 3 1 32 72
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Identification Codes
INSTRUCTION EXTEST IDCODE SAMPLE Z RESERVED SAMPLE/PRELOAD CODE 000 001 010 011 100 DESCRIPTION Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM outputs to High-Z state. This instruction is not 1149.1 compliant. Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operations. Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a High-Z state. Do Not Use: This instruction is reserved for future use. Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does not affect SRAM operation. This instruction does not implement 1149.1 preload function and is therefore not 1149.1 compliant. Do Not Use: This instruction is reserved for future use. Do Not Use: This instruction is reserved for future use. Places the bypass register between TDI and TDO. This operation does not affect SRAM operations.
RESERVED RESERVED BYPASS
101 110 111
119-Ball BGA Boundary Scan Order CY7C1381CV25 (512K x 36)
BIT# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 BALL ID K4 H4 M4 F4 B4 A4 G4 C6 A6 D6 D7 E6 G6 H7 E7 F6 G7 H6 T7 K7 L6 N6 P7 K6 L7 M6 N7 P6 BIT# 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 BALL ID B2 P4 N4 R6 T5 T3 R2 R3 P2 P1 N2 L2 K1 N1 M2 L1 K2 Not Bonded (Preset to 0) H1 G2 E2 D1 H2 G1 F2 E1 D2 A5 Page 20 of 35
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CY7C1381CV25 CY7C1383CV25
119-Ball BGA Boundary Scan Order (continued)
29 30 31 32 33 34 35 36 BIT# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 B5 B3 C5 C3 C2 A2 T4 B6 BALL ID K4 H4 M4 F4 B4 A4 G4 C6 A6 T6 Not Bonded (Preset to 0) Not Bonded (Preset to 0) Not Bonded (Preset to 0) D6 E7 F6 G7 H6 T7 K7 L6 N6 P7 Not Bonded (Preset to 0) Not Bonded (Preset to 0) Not Bonded (Preset to 0) Not Bonded (Preset to 0) Not Bonded (Preset to 0) B5 B3 C5 C3 C2 A2 T2 B6 65 66 67 68 69 70 71 72 BIT# 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 A3 E4 Internal L3 G3 G5 L5 Internal BALL ID B2 P4 N4 R6 T5 T3 R2 R3 Not Bonded (Preset to 0) Not Bonded (Preset to 0) Not Bonded (Preset to 0) Not Bonded (Preset to 0) P2 N1 M2 L1 K2 Internal H1 G2 E2 D1 Not Bonded (Preset to 0) Not Bonded (Preset to 0) Not Bonded (Preset to 0) Not Bonded (Preset to 0) Not Bonded (Preset to 0) A5 A3 E4 Internal Not Bonded (Preset to 0) Internal G3 L5 Internal
CY7C1383CV25 (1M x 18)
Document #: 38-05241 Rev. *B
Page 21 of 35
CY7C1381CV25 CY7C1383CV25
165-Ball fBGA Boundary Scan Order CY7C1381CV25 (512K x 36)
BIT# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 BALL ID B6 B7 A7 B8 A8 B9 A9 B10 A10 C11 E10 F10 G10 D10 D11 E11 F11 G11 H11 J10 K10 L10 M10 J11 K11 L11 M11 N11 R11 R10 R9 R8 P10 P9 P8 P11 BIT# 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 BALL ID N6 R6 P6 R4 R3 P4 P3 R1 N1 L2 K2 J2 M2 M1 L1 K1 J1 Not Bonded (Preset to 0) G2 F2 E2 D2 G1 F1 E1 D1 C1 A2 B2 A3 B3 B4 A4 A5 B5 A6
Document #: 38-05241 Rev. *B
Page 22 of 35
CY7C1381CV25 CY7C1383CV25
165-Ball fBGA Boundary Scan Order (continued) CY7C1383CV25 (1M x 18)
BIT# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 BALL ID B6 B7 A7 B8 A8 B9 A9 B10 A10 A11 Not Bonded (Preset to 0) Not Bonded (Preset to 0) Not Bonded (Preset to 0) C11 D11 E11 F11 G11 H11 J10 K10 L10 M10 Not Bonded (Preset to 0) Not Bonded (Preset to 0) Not Bonded (Preset to 0) Not Bonded (Preset to 0) Not Bonded (Preset to 0) R11 R10 R9 R8 P10 P9 P8 P11 BIT# 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 BALL ID N6 R6 P6 R4 R3 P4 P3 R1 Not Bonded (Preset to 0) Not Bonded (Preset to 0) Not Bonded (Preset to 0) Not Bonded (Preset to 0) N1 M1 L1 K1 J1 Not Bonded (Preset to 0) G2 F2 E2 D2 Not Bonded (Preset to 0) Not Bonded (Preset to 0) Not Bonded (Preset to 0) Not Bonded (Preset to 0) Not Bonded (Preset to 0) A2 B2 A3 B3 Not Bonded (Preset to 0) Not Bonded (Preset to 0) A4 B5 A6
Document #: 38-05241 Rev. *B
Page 23 of 35
CY7C1381CV25 CY7C1383CV25
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage on VDD Relative to GND........ -0.3V to +4.6V DC Voltage Applied to Outputs in Tri-State........................................... -0.5V to VDDQ + 0.5V DC Input Voltage....................................-0.5V to VDD + 0.5V Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage........................................... >2001V (per MIL-STD-883, Method 3015) Latch-up Current..................................................... >200 mA
Operating Range
Ambient Range Temperature Commercial 0C to +70C Industrial -40C to +85C VDD 2.5V +/- 5% VDDQ 2.5V - 5% to VDD
Electrical Characteristics Over the Operating Range[12, 13]
Parameter VDD VDDQ VOH VOL VIH VIL IX Description Power Supply Voltage I/O Supply Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Voltage[12] Input LOW Voltage[12] Input Load Test Conditions VDDQ = 2.5V VDDQ = 2.5V, VDD = Min., IOH = -1.0 mA VDDQ = 2.5V, VDD = Min., IOL = 1.0 mA VDDQ = 2.5V VDDQ = 2.5V GND VI VDDQ Input = VDD Input Current of ZZ IOZ IOS IDD Input = VSS Input = VDD Output Leakage Current GND VI VDD, Output Disabled Output Short Circuit Current VDD Operating Supply Current Automatic CE Power-down Current--TTL Inputs VDD = Max., VOUT = GND VDD = Max., IOUT = 0 mA, f = fMAX = 1/tCYC Max. VDD, Device Deselected, VIN VIH or VIN VIL, f = fMAX, inputs switching 7.5-ns cycle, 133 MHz 8.8-ns cycle, 117 MHz 10-ns cycle, 100 MHz ISB1 7.5-ns cycle, 133 MHz 8.8-ns cycle, 117 MHz 10-ns cycle, 100 MHz All speeds -5 -30 30 5 -300 210 190 175 120 110 100 70 mA Min. 2.375 2.375 2.0 1.7 -0.3 -5 -30 30 Max. 2.625 VDD 0.4 VDD + 0.3V 0.7 5 Unit V V V V V V A A A A A A A mA mA mA mA mA
Input Current of MODE Input = VSS
ISB2 ISB3
Automatic CE Max. VDD, Device Deselected, Power-down VIN VDD - 0.3V or VIN 0.3V, Current--CMOS Inputs f = 0, inputs static Automatic CE Max. VDD, Device Deselected, Power-down VIN VDDQ - 0.3V or VIN 0.3V, Current--CMOS Inputs f = fMAX, inputs switching Automatic CE Power-down Current--TTL Inputs Max. VDD, Device Deselected, VIN VDD - 0.3V or VIN 0.3V, f = 0, inputs static
7.5-ns cycle, 133 MHz 8.8-ns cycle, 117 MHz 10-ns cycle, 100 MHz All Speeds
105 100 95 80
mA mA mA mA
ISB4
Notes: 12. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC) > -2V (Pulse width less than tCYC/2). 13. TPower-up: Assumes a linear ramp from 0v to VDD(min.) within 200ms. During this time VIH < VDD and VDDQ < VDD
Document #: 38-05241 Rev. *B
Page 24 of 35
CY7C1381CV25 CY7C1383CV25
Thermal Resistance[14]
Parameter Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA / JESD51. TQFP Package 31 6 BGA Package 45 7 fBGA Package 46 3 Unit C/W C/W
JA JC
Capacitance[14]
Parameter CIN CCLK CI/O Description Input Capacitance Clock Input Capacitance Input/Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VDD = 2.5V. TQFP Package 5 5 5 BGA Package 8 8 8 fBGA Package 9 9 9 Unit pF pF pF
Notes: 14. Tested initially and after any design or process change that may affect these parameters
AC Test Loads and Waveforms
2.5V I/O Test Load
OUTPUT Z0 = 50 2.5V OUTPUT RL = 50 VL = 1.25V R = 1667 VDD 5 pF GND R =1538 10% ALL INPUT PULSES 90% 90% 10% 1ns
1ns
(a)
INCLUDING JIG AND SCOPE
(b)
(c)
Document #: 38-05241 Rev. *B
Page 25 of 35
CY7C1381CV25 CY7C1383CV25
Switching Characteristics Over the Operating Range[19, 20]
133 MHz Parameter tPOWER Clock tCYC tCH tCL Output Times tCDV tDOH tCLZ tCHZ tOEV tOELZ tOEHZ Setup Times tAS tADS tADVS tWES tDS tCES Hold Times tAH tADH tWEH tADVH tDH tCEH Address Hold After CLK Rise ADSP, ADSC Hold After CLK Rise GW,BWE, BW[A:D] Hold After CLK Rise ADV Hold After CLK Rise Data Input Hold After CLK Rise Chip Enable Hold After CLK Rise 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 ns ns ns ns ns ns Address Set-up Before CLK Rise ADSP, ADSC Set-up Before CLK Rise ADV Set-up Before CLK Rise GW, BWE, BW[A:D] Set-up Before CLK Rise Data Input Set-up Before CLK Rise Chip Enable Set-up 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 ns ns ns ns ns ns Data Output Valid After CLK Rise Data Output Hold After CLK Rise Clock to Low-Z[16, 17, 18] Clock to High-Z[16, 17, 18] OE LOW to Output Valid OE LOW to Output Low-Z[16, 17, 18]
[16, 17, 18]
117 MHz Min. 1 8.5 2.3 2.3 Max.
100 MHz Min. 1 10 2.5 2.5 Max. Unit ms ns ns ns 8.5 2.0 2.0 ns ns ns 5.0 3.8 0 5.0 ns ns ns ns
Description VDD(Typical) to the first Access Clock Cycle Time Clock HIGH Clock LOW
[15]
Min. 1 7.5 2.1 2.1
Max.
6.5 2.0 2.0 0 0 4.0 4.0 3.2 0 2.0 2.0 0
7.5
4.0 3.4 4.0
0
OE HIGH to Output High-Z
Notes: 15. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially, before a read or write operation can be initiated. 16. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured 200 mV from steady-state voltage. 17. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High-Z prior to Low-Z under the same system conditions 18. This parameter is sampled and not 100% tested. 19. Timing reference level is 1.25V. 20. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
Document #: 38-05241 Rev. *B
Page 26 of 35
CY7C1381CV25 CY7C1383CV25
Timing Diagrams
Read Cycle Timing[21]
tCYC
CLK
t
CH
t CL
tADS
tADH
ADSP
tADS tADH
ADSC
tAS tAH
ADDRESS
A1
t WES t WEH
A2
GW, BWE,BW
X tCES t CEH
Deselect Cycle
CE
t t ADVS ADVH
ADV ADV suspends burst OE
t OEV t CLZ t OEHZ t OELZ
tCDV tDOH t CHZ
Data Out (Q)
High-Z
Q(A1)
t CDV
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Burst wraps around to its initial state
Single READ DON'T CARE
BURST READ UNDEFINED
Notes: 21. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
Document #: 38-05241 Rev. *B
Page 27 of 35
CY7C1381CV25 CY7C1383CV25
Timing Diagrams (continued)
Write Cycle Timing[21, 22]
t CYC
CLK
t
CH
t
CL
tADS
tADH
ADSP
tADS tADH
ADSC extends burst
tADS tADH
ADSC
tAS tAH
ADDRESS
A1
A2
Byte write signals are ignored for first cycle when ADSP initiates burst
A3
tWES tWEH
BWE, BWX
t t WES WEH
GW
tCES tCEH
CE
tADVS tADVH
ADV
ADV suspends burst
OE
t DS t DH D(A2) D(A2 + 1) D(A2 + 1) D(A2 + 2) D(A2 + 3) D(A3) D(A3 + 1) D(A3 + 2)
Data in (D)
High-Z
t OEHZ
D(A1)
Data Out (Q) BURST READ Single WRITE BURST WRITE Extended BURST WRITE
DON'T CARE
UNDEFINED
Notes: 22. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BWX LOW.
4
Document #: 38-05241 Rev. *B
Page 28 of 35
CY7C1381CV25 CY7C1383CV25
Timing Diagrams (continued)
Read/Write Cycle Timing[21, 23, 24]
tCYC
CLK
t CH tADS tADH
t CL
ADSP
ADSC
tAS tAH
ADDRESS
A1
A2
A3
t t WES WEH
A4
A5
A6
BWE, BWX
tCES tCEH
CE
ADV
OE
tDS tDH tOELZ
Data In (D) Data Out (Q)
High-Z
t OEHZ
D(A3)
tCDV
D(A5)
D(A6)
Q(A1)
Q(A2) Single WRITE DON'T CARE
Q(A4)
Q(A4+1)
Q(A4+2)
Q(A4+3) Back-to-Back WRITEs
Back-to-Back READs
BURST READ UNDEFINED
Note: 23. The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC. 24. GW is HIGH.
Document #: 38-05241 Rev. *B
Page 29 of 35
CY7C1381CV25 CY7C1383CV25
Timing Diagrams (continued)
ZZ Mode Timing [25, 26]
CLK
t ZZ t ZZREC
ZZ
t ZZI
I
SUPPLY I DDZZ t RZZI DESELECT or READ Only
ALL INPUTS (except ZZ)
Outputs (Q)
High-Z
DON'T CARE
Notes: 25. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device. 26. DQs are in high-Z when exiting ZZ sleep mode.
Document #: 38-05241 Rev. *B
Page 30 of 35
CY7C1381CV25 CY7C1383CV25
Ordering Information
Speed (MHz) 133 Ordering Code CY7C1381CV25-133AC CY7C1383CV25-133AC CY7C1381CV25-133BGC CY7C1383CV25-133BGC CY7C1381CV25-133BZC CY7C1383CV25-133BZC 117 CY7C1381CV25-117AC CY7C1383CV25-117AC CY7C1381CV25-117BGC CY7C1383CV25-117BGC CY7C1381CV25-117BZC CY7C1383CV25-117BZC CY7C1381CV25-117AI CY7C1383CV25-117AI CY7C1381CV25-117BGI CY7C1383CV25-117BGI CY7C1381CV25-117BZI CY7C1383CV25-117BZI 100 CY7C1381CV25-100AC CY7C1383CV25-100AC CY7C1381CV25-100BGC CY7C1383CV25-100BGC CY7C1381CV25-100BZC CY7C1383CV25-100BZC CY7C1381CV25-100AI CY7C1383CV25-100AI CY7C1381CV25-100BGI CY7C1383CV25-100BGI CY7C1381CV25-100BZI CY7C1383CV25-100BZI BB165A BG119 A101 BB165A BB165A A101 BG119 BB165A A101 BG119 BG119 Package Name A101 BG119 BB165A A101 Part and Package Type 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm) 3 Chip Enables 119-ball (14 x 22 x 2.4 mm) BGA 3 Chip Enables and JTAG 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.2mm) 3 Chip Enables and JTAG 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm) 3 Chip Enables 119-ball (14 x 22 x 2.4 mm) BGA 3 Chip Enables and JTAG 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.2mm) 3 Chip Enables and JTAG 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm) 3 Chip Enables 119-ball (14 x 22 x 2.4 mm) BGA 3 Chip Enables and JTAG 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.2mm) 3 Chip Enables and JTAG 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm) 3 Chip Enables 119-ball (14 x 22 x 2.4 mm) BGA 3 Chip Enables and JTAG 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.2mm) 3 Chip Enables and JTAG 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm) 3 Chip Enables 119-ball (14 x 22 x 2.4 mm) BGA 3 Chip Enables and JTAG 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.2mm) 3 Chip Enables and JTAG Industrial Commercial Industrial Commercial Operating Range Commercial
Shaded areas contain advance information. Please contact your local sales representative for availability of these parts.
Document #: 38-05241 Rev. *B
Page 31 of 35
CY7C1381CV25 CY7C1383CV25
Package Diagrams
100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
16.000.20 14.000.10
100 1 81 80
DIMENSIONS ARE IN MILLIMETERS.
1.400.05
0.300.08
22.000.20
20.000.10
0.65 TYP.
30 31 50 51
121 (8X)
SEE DETAIL
A
0.20 MAX. 1.60 MAX. STAND-OFF 0.05 MIN. 0.15 MAX.
0.10
R 0.08 MIN. 0.20 MAX.
0 MIN.
0.25 GAUGE PLANE R 0.08 MIN. 0.20 MAX.
SEATING PLANE
0-7 0.600.15
0.20 MIN. 1.00 REF.
DETAIL
A
51-85050-*A
Document #: 38-05241 Rev. *B
Page 32 of 35
CY7C1381CV25 CY7C1383CV25
Package Diagrams (continued)
119-Lead PBGA (14 x 22 x 2.4 mm) BG119
51-85115-*B
Document #: 38-05241 Rev. *B
Page 33 of 35
CY7C1381CV25 CY7C1383CV25
Package Diagrams (continued)
165-Ball FBGA (13 x 15 x 1.2 mm) BB165A
51-85122-*C
i486 is a trademark, and Intel and Pentium are registered trademarks of Intel Corporation. PowerPC is a trademark of IBM Corporation. All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05241 Rev. *B
Page 34 of 35
(c) Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. Cypress products are not warranted nor intended to be used for medical, life-support, life-saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress.
CY7C1381CV25 CY7C1383CV25
Document History Page
Document Title: CY7C1381CV25/ CY7C1383CV2518-Mbit (512K x 36/1M x 18) Flow-Through SRAM Document #: 38-05241 Rev. *B REV. ** *A *B ECN NO. 116281 206081 225181 Issue Date 08/28/02 See ECN See ECN Orig. of Change SKX RKF VBL New Data Sheet Final Data Sheet Update Ordering Info section: shade all part numbers Correct in feature page, core power supply tolerance to +/-5% Description of Change
Document #: 38-05241 Rev. *B
Page 35 of 35

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